1. Field of the Invention
The present invention relates to a flat panel display device and, more particularly, an active matrix type display device in which a switching element is provided to each display pixel.
2. Description of the Related Art
The flat panel display device being represented by the liquid crystal display device is utilized in various fields because it is thin and light in weight and low power consumption. Since the active matrix type liquid crystal display device in which switching elements are provided to the display pixels respectively can suppress cross-talk between neighboring display pixels to the lowest minimum, it is utilized in the fields in which the high definition display images are required particularly.
In the active matrix type liquid crystal display device which is spread commonly at present, a twisted nematic (TN) type liquid crystal is held between an array substrate and an opposing substrate via alignment films. A plurality of scanning lines and a plurality of signal lines are arranged mutually in a matrix fashion via an insulating film on the array substrate. Switching elements such as thin film transistors (TFTs), etc. are arranged in the vicinity of the intersections of respective lines, and then pixel electrodes are arranged via the switching elements. Also, opposing electrodes are arranged on the opposing substrate so as to oppose to the pixel electrodes.
In such liquid crystal display device, in order to prevent an event that electrical charges stored in the liquid crystal capacitances Clc are leaked through the switching elements to thus degrade display quality, auxiliary capacitances Cs are connected in parallel with the liquid crystal capacitances Clc of respective display pixels. There are two types of the array substrate configurations to which the auxiliary capacitances Cs are connected. One is the independent Cs line type array substrate in which auxiliary capacitance lines are provided in substantially parallel with the scanning lines and overlapped with pixel electrode via the insulating film so as to form the capacitance between the pixel electrode and the auxiliary capacitance line. The other is the Cs-on gate type array substrate in which the capacitance is formed between the scanning line at the preceding stage and the pixel electrode, which is arranged to be partially overlapped via the insulating film, along the scanning direction. The Cs-on gate type array substrate has such an advantages that, since unnecessary wirings like the auxiliary capacitances line can be omitted, a higher aperture ratio can be achieved.
However, according to the Cs-on gate type device, since the pixel electrodes are overlapped partially with the scanning line provided to the preceding stage, there is such a problem that flicker becomes obvious particularly in the high definition liquid crystal display device. The cause of the flicker will be explained hereunder.
FIG. 1 is an equivalent circuit diagram of pixels of a conventional Cs-on gate type device. TFT (i, j) and TFT (i, j+1) are arranged as switching elements in the vicinity of intersections between the signal line Xi and the scanning lines Yj, Yj+1. Drain electrodes of the TFTs are connected to the signal line Xi, and gate electrodes of the TFTs are connected to the scanning lines Yj, Yj+1 respectively. Also, source electrodes of the TFTs are connected to the pixel electrodes E respectively. A liquid crystal layer LC is held between the pixel electrodes E and opposing electrodes C. A liquid crystal capacitances Clc is formed by this liquid crystal layer LC. An auxiliary capacitance Cs is connected between the pixel electrode E and the neighboring scanning line in electrically parallel with the liquid crystal capacitance Clc.
Next, the case where horizontal pixel lines are sequentially scanned from the top will be explained with reference to a display pixel which is provided to an intersection portion between the signal line Xi and the scanning line Yj.
FIG. 2 is a voltage waveform diagram showing waveforms of pulses which are applied to the signal lines and the scanning lines in FIG. 1. In FIG. 2, VXi denotes a signal pulse which is applied to the signal line Xi, and VYj, VYj+1 denote scanning pulses which are applied to the scanning lines Yj, Yj+1 respectively. As shown in FIG. 1, various parasitic capacitances such as a gate-drain capacitance Cgd of the TFT (i, j), a scanning line-pixel electrode capacitance Cgs including a gate-source capacitance of the TFT (i, j), a signal line-scanning line capacitance Cg_s, a scanning line-opposing electrode capacitance Cg_c, etc. in addition to its own wiring resistance are present on the scanning line Yj. Therefore, the trailing edge of the scanning pulse VYj which is applied from the scanning line Yj to a gate of the TFT becomes gentle due to an influence of various parasitic capacitances and is deviated from an ideal waveform which is indicated by a broken line in FIG. 2. Thus, the leading edge/the trailing edge of the waveform is delayed, as shown by a solid line in FIG. 2.
In the event that the scanning pulse VYj is applied to the scanning line Yj and also the scanning line Yj+1 provided at the succeeding stage is not turned on until the scanning pulse VYj is reduced below a threshold value of the TFT (i, j), the liquid crystal capacitance Clc at the succeeding stage and the auxiliary capacitance Cs are connected in series with each other to the scanning line Yj. At this time, for example, the capacitance connected to the scanning line Yj can be given by EQU Cgd+Cgs+Cg_s+Cg_c+{Cs.multidot.Clc/Cs+Clc} 1
However, in the event that delay of the scanning pulse is caused and also the TFT (i, j+1) of the scanning line Yj+1 provided at the succeeding stage is turned on before the scanning pulse VYj is reduced below the threshold value (Vth) of the TFT (i, j), for example, the capacitance connected to the scanning line Yj can be given by EQU Cgd+Cgs+Cg_s+Cg_c+Cs 2
This capacitance is increased rather than that given by Eq. (1).
In this manner, in the Cs-on gate type liquid crystal display device, if on-periods of the TFTs are overlapped effectively between neighboring scanning lines Yj and Yj+1, the capacitance coupled to the scanning line Yj is increased and thus a waveform of the scanning pulse VYj is further delayed. In particular, in the high precision liquid crystal display device, if one horizontal scanning period becomes shorter, an interval between the scanning pulses is also reduced and thus the on-periods of the TFTs are ready to overlap with each other. In addition, since the numbers of the TFTs, etc. are increased, parasitic capacitances are increased and thus delay of the scanning pulse VYj is accelerated. Therefore, according to the liquid crystal display device in the prior art, with the progress of high definition, considerable difference in a delay amount of the scanning pulse is caused between the power supply side of the scanning pulse VYj and the end point side because of the above reason, and therefore deterioration of display quality such as flicker, etc. is easily generated.